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january 2013 doc id 024199 rev 1 1/29 AN4243 application note the l6230 dmos driver for three-phase brushless dc motor by cristiana scaramel introduction modern motion control applications need more flexibility that can be only addressed with specialized ics products. the l6230 is a dmos fully integrated three-phase bldc motor driver optimized for field oriented control (foc) application thanks to the independent current senses. the device integrates six dmos power transistors with cmos and bipolar circuits on the same chip including overcurrent protection for safe operation and flexibility. an uncommitted comparator with open-drain output for optional function is available. www.st.com
contents AN4243 2/29 doc id 024199 rev 1 contents 1 l6230 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 designing an application with the l6230 . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 current ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 voltage ratings and operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 choosing the bulk capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 sensing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 charge pump external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 sharing the charge pump circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8 how to generate a reference voltage for the current control . . . . . . . . . . 12 2.9 input logic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.11 thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 brake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 23 3.3 six-step driving method with bemf zero crossing detection . . . . . . . . . . 24 4 demonstration boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 eval6230qr demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 steval-ifn003v1:pmsm foc motor driver based on the l6230 and stm32f103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 steval-ifn004v1:bldc six-step motor driver based on the l6230 and stm8s105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AN4243 l6230 block diagram doc id 024199 rev 1 3/29 1 l6230 block diagram the l6230 (see figure 1 ) includes logic for cmos/ttl interface, a charge pump that provides auxiliary voltage to drive the high-side dmos, non-dissipative overcurrent protection circuitry on the high-side dmos, with a fixed trip point set at 2.8 a (see section 2.10 ), overtemperature protection, undervoltage lockout for reliable startup. figure 1. l6230 block diagram charge pump voltage regulator thermal protection ocd1 ocd ocd2 10v 5v vcp vs a gate logic vboot v boot out 1 out 2 sense 1 2 vs b out 3 sense 3 diag-en in 1 in 3 en 3 en 2 cp+ in 2 ocd3 v boot ocd1 10v v boot ocd2 10v v boot ocd3 10v comparator + - cp- cpout sense en 1 am1656 3 v1
designing an application with the l6230 AN4243 4/29 doc id 024199 rev 1 2 designing an application with the l6230 2.1 current ratings with mosfet (dmos) devices, unlike bipolar transistors, the current under short-circuit conditions is, at first approximation, limited by the r ds(on) of the dmos themselves and could reach very high values. the l6230 out pins and the two v sa and v sb pins are rated for a maximum of 1.4 a r.m.s and 2.8 a peak (typical values). these values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. in practical applications, maximum allowable current is less than these limits; actually the constraint is the power dissipation. the device integrates overcurrent detection (ocd) that provides protection against short-circuits between the outputs and between an output and ground (see section 2.10 ). 2.2 voltage ratings and operating range the l6230 requires a single supply voltage (v s ), for the motor supply. internal voltage regulators provide the 5 v and 10 v required for the internal circuitry. the operating range for v s is from 8 to 52 v. to prevent from working into undesirable low voltage supply an undervoltage lockout (uvlo), circuit shuts down the device when supply voltage falls below 6 v; to resume normal operating conditions, v s must then exceed 6.8 v. the hysteresis is provided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that dmos's r ds(on) is a function of the v s supply voltage. actually, when v s is less than 10 v, r ds(on) is adversely affected, and this is particularly true for the high-side dmos that are driven from vboot supply. this supply is obtained through a charge pump from the internal 10 v supply, which tends to reduce its output voltage when v s goes below 10 v. figure 2 shows the supply voltage of the high-side gate drivers (vboot - v s ) versus the supply voltage (v s ). figure 2. supply voltage of high-side gate drivers versus supply voltage
AN4243 designing an application with the l6230 doc id 024199 rev 1 5/29 note that v s must be connected to both v sa and v sb since the bootstrap voltage (at vboot pin) is the same as the three half-bridges. the integrated dmos have a rated drain- source breakdown voltage of 60 v. however v s should be kept below 52 v, since, in normal working conditions, the dmos see a v ds voltage that exceeds the v s supply. in particular, when a high-side dmos turns off due to a phase change (out1 in figure 3 ), if one of the other outputs (out2 in figure 3 ) is high, the load current starts flowing in the low-side freewheeling diode and the sense pin sees a negative spike due to a non-negligible parasitic inductance of the pcb path from the pin to gnd. this spike is followed by a stable negative voltage due to the drop on r sense . the out pin sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it. typical duration of this spike is 30 ns. at the same time, the out2 pin (in the example of figure 3 ) sees a voltage above v s , due to voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. it turns out that the highest differential voltage is observed between two out pins when a phase change turns a high-side off, and this must always be kept below 60 v. figure 3. currents and voltages if a phase change turns a high-side off during off- time figure 4 shows the voltage waveforms at the out pins referring to a possible practical situation, with a peak output current of 1.4 a, v s = 52 v, r sense = 0.33 , t j = 25 oc (approximately) and a good pcb layout. below ground spike amplitude is -2.65 v for one output, the other out pin is at about 55 v. in these conditions, total differential voltage reaches almost 60 v, which is the absolute maximum rating for the dmos. keeping differential voltage between two output pins within rated values is a must that can be accomplished with proper selection of bulk capacitor value and equivalent series resistance (esr), according to the current peaks and adopting good layout practices to minimize pcb parasitic inductances. on- me off - me d u ring off- me a ph as e ch a nge c a n occ u r c b p a r as i c ind u ct a nce r s en s e *i r s en s e *i+v f(diode) b u lk c a p a citor e qu iv a lent circ u it e s r e s l pcb p a r as i c ind u ct a nce v s c u rrent s t a rt s ? owing in the thir d h a lf b ridge am16565v1
designing an application with the l6230 AN4243 6/29 doc id 024199 rev 1 figure 4. voltage at the two outputs if a phase change turns a high-side off 2.3 choosing the bulk capacitor since the bulk capacitor, placed between v s and gnd pins, is charged and discharged during ic operation, its ac current capability must be greater than the rms value of the charge/discharge current. this current flows from the capacitor to the ic during the on-time (t on ) and from the ic (implementing a fast decay current recirculation technique) or from the power supply (implementing a slow decay current recirculation technique) to the capacitor during the off-time (t off ). the rms value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty cycle. it also depends on power supply characteristics. a power supply with poor high-frequency performances (or long, inductive connections to the ic) causes the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor. rms current in the capacitor, however, does not exceed the rms output current. bulk capacitor value (c) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. in slow decay, neglecting the deadtime and output current ripple and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is: am16566v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 7/29 equation 1 so the supply voltage ripple is: equation 2 where i out is the output current. with fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. this can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52 v). in fast decay the supply voltage ripple is about: equation 3 always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the deadtime. usually (if c > 100 f) the capacitance role is much less than the esr, then supply voltage ripple can be estimated as: equation 4 equation 5 for example, if a maximum ripple of 500 mv is allowed and i out = 1 a, the capacitor esr should be lower than: equation 6 equation 7 actually, current, sunk by v sa and v sb pins of the device, is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. the duration of these peaks is, tough, very short and can be filtered using a small value (100 200 nf), good quality ceramic capacitor, connected as close as possible to the v sa , v sb and gnd pins of the ic. the bulk capacitor is chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. v s i out esr t on c ------ - + ?? ?? ? ? v s i out esr t on c ------ - + ?? ?? ? ? i out 2esr t on t off + c --------------------------- + ? ?? ?? ? ? ? ------------ 500m in slow decay = < -- - 0.5v 1a ------------ ? 250 500 () m in fast decay = <
designing an application with the l6230 AN4243 8/29 doc id 024199 rev 1 for example, with a 48 v nominal power supply, with 5% tolerance, maximum voltage is 50.4 v, then operating voltage for the capacitor should be at least 63 v. 2.4 layout considerations working with devices that combine high power switches and control logic in the same ic, special attention has to be paid to the pcb layout. in extreme cases, power dmos commutation can induce noises that could cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic connections, especially high-impedance nodes (actually all logic input, see further), must be kept far from switching nodes and paths. with the l6230, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600 khz). the primary means to minimize conducted noise is to have a good gnd layout (see figure 5 ). figure 5. typical application and layout suggestions high-current gnd tracks (i.e. the tracks connected to the sensing resistor) must be connected directly to the negative terminal of the bulk capacitor. a good quality, high frequency bypass capacitor is also required (typically from 100 nf to 200 nf ceramic would suffice), since electrolytic capacitors show a poor high frequency performance. both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to v sa , v sb and gnd. on the l6230, gnd pins are the logic ground, since only the quiescent current flows through them. logic ground and power ground should be connected together in a single point, the bulk capacitor, to avoid the power ground noise from affecting the logic ground. layouting the path from the sense pins through the sensing resistor to the negative terminal of the bulk capacitor (power ground) requires particular attention. these tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on sense and out pins (see section 2.2 ). for the same reason, the capacitors on v sa , v sb and gnd pins should be very close to the gnd and supply pins. refer to the section 2.5 for information on selecting the sense resistors. traces connected to v sa , v sb , sensea, senseb, and the three out pins must be designed with adequate width, since high-currents are flowing through these traces, and layer changes should be + - v s = 8 52 v diag/en en2 en1 in 3 in2 in1 cp- gnd gnd gnd gnd s en s e s en s e v s a v s b v boot cp out 3 out 1 out 2 d1 d2 ren r5 cen c1 c b oo c?y c2 l62 3 0 + - logic su pply en 3 cp+ microcontroller rcp ccp cpout ccpo u t rcpo u t vp u ll s en s e1 am16567v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 9/29 avoided. should a layer change be necessary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve power dissipation for the device. figure 6 shows two typical situations that must be avoided. an important consideration about the location of the bulk capacitor is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 6 prevents the recirculation current from reaching the capacitors and results in a high voltage on the ic pins that can damage the device. having a switch or a power connection that can disconnect the capacitors from the ic, while there is still current in the motor, also results in a high-voltage transient since there is no capacitance to absorb the recirculation current. figure 6. layout suggestions 2.5 sensing resistor each motor winding current flows through the sensing resistors, causing a voltage drop that is used to control the peak value of the load current. two issues must be taken into account when choosing the r sense value. the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pins during the current recirculation. for this reason, the resistance of this component should be kept low. the voltage drop across r sense can be compared to a reference voltage. the lower is the r sense value, the higher is the peak current error due to noise input and to the input offset of the current sense comparator: too small values of r sense must be avoided. a good compromise is to calculate the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (i peak ), is about 0.5 v: equation 8 gnd gnd gnd gnd s en s e s en s e v s a v s b r5 c1 c 8 c2 l62 3 0 do not connect the logic gnd here volt a ge drop d u e to c u rrent in s en s e p a th c a n di s t u r b logic gnd do not p u t a diode here! recirc u l a ting c u rrent c a nnot ?ow into the bu lk c a p a citor a nd c aus e s a high volt a g e s pike th a t c a n d a m a ge the ic s en s e 3 am1656 8 v1 r sense 0.5v i peak ------------ - =
designing an application with the l6230 AN4243 10/29 doc id 024199 rev 1 it should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous negative spikes on sense pins. wire wounded resistors cannot be used here, while metallic film resistors are recommended for their high peak current capability and low inductance. for the same reason the connections between the sense pins, c1, c2, v sa , v sb and gnd pins (see figure 6 ) must be taken as short as possible (see section 2.4 ). the average power dissipated by the sensing resistor is: fast decay recirculation: slow decay recirculation: where d is the duty cycle of the pwm current control, i rms is the rms value of the load current. nevertheless, the sensing resistor power rating should be chosen, taking into account the peak value of the dissipated power: equation 9 where i pk is the peak value of the load current. multiple resistors in parallel help to obtain the required power rating with standard resistors, and reduce the inductance. the r sense tolerance reflects on the peak current error: 1% resistors should be preferred. ta b l e 1 shows r sense recommended values () for a 0.5 v drops and power ratings for typical rms and peak current values 2.6 charge pump external components an internal oscillator, with its output at cp pin, switches from gnd to 10 v with a typical frequency of 600 khz (see figure 1 ). table 1. r sense recommended values i pk [a] r sense [ ] r sense power rating [w] alternatives 0.25 2 0.125 0.5 1 0.25 1 0.5 0.5 2 x 1 , 0.25 w paralleled p r i rms 2 r sense ? ? ?? ? ? ?
AN4243 designing an application with the l6230 doc id 024199 rev 1 11/29 figure 7. charge pump circuitry when the oscillator output is at ground, c fly is charged by v s through d2. when it rises to 10 v, d2 is reverse biased and the charge flows from c fly to c boot through d1, so the v boot pin, after some few cycles, reaches the maximum voltage of v s + 10 v v d1 v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9 v and both the bridges switching at 50 khz, the typical current drawn by the v boot pin is 1.85 ma. care must be taken to develop the pcb layout of c fly , d1, d2 connections in order to minimize interferences with the rest of the circuit (see also the section 2.4 ). recommended values for the charge pump circuitry are: d1, d2 : 1n4148 c fly : 10 nf - 100v (ceramic capacitor) c boot : 220 nf - 35v (ceramic capacitor) due to the high charge pump frequency, fast diodes are required. connecting the cold side of the bulk capacitor (c2) to v s instead of gnd, the average current in the external diodes during operation is less than 10 ma. at ic power-up the current in the external diodes during operation is less than 200 ma. the reverse voltage is about 10 v in all conditions. the 1n4148 diodes withstand about 200 ma dc (1 a peak), and the maximum reverse voltage is 75 v, so they should fit for the majority of applications. l62 3 0 v s - v d1 f = 600 k h v s a v s b v boot cp d1 d2 c b oot c? y 10 v 10 v to high- s ide 1 0 v f = 600 k h ch a rge p u mp o s cill a tor v s + 10 v - v d1 - v d2 v s + 10 v - v d1 am16569v1
designing an application with the l6230 AN4243 12/29 doc id 024199 rev 1 2.7 sharing the charge pump circuitry if more than one device is used in the application, it is possible to use the charge pump from one l6230 to supply the v boot pins of several ics. the unused cp pins on the slave devices are left unconnected, as shown in figure 8 . a 100 nf capacitor (c boot2 ) should be connected to the v boot pin of each device. supply voltage pins (v s ) of the devices sharing charge pump must be connected together. the higher the number of devices sharing the same charge pump, the lower the differential voltage available for gate drive (v boot - v s ), causing a higher r ds(on) for the high-side dmos, so higher dissipating power. a better performance can also be obtained using a 33 nf capacitor for c fly and using schottky diodes (for example bat47 are recommended). sharing the same charge pump circuitry for more than 3 or 4 devices is not recommended, since it reduces the v boot voltage increasing the high-side mos on-resistance and thus power dissipation. figure 8. sharing the charge pump circuitry 2.8 how to generate a reference voltage for the current control the device has an analog input (cp-) connected to the internal comparator, that can be used to control the peak value of the motor current through an external control loop. a fixed reference voltage can be easily obtained with a resistive divider from an available pull-up voltage rail (maybe the one supplying the microcontroller or the rest of the application) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c ( figure 9 ). l62 3 0 v s a v s b v boot cp d1 d2 c b oot2 c? y 1 to high - s ide l62 3 0 v s a v s b v boot c b oot1 to high - s ide to other device s l62 3 0 cp am16570v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 13/29 figure 9. obtaining a reference voltage through a pwm output of microcontroller assuming that this output swings from 0 to 5v, the resulting average voltage is: equation 10 where dc is the duty cycle of the pwm output of the microcontroller. assuming that the microcontroller output impedance is lower than 1 k , with r cp1 = 5.6 k , r cp2 = 1.5 k, c cp = 100 nf and a pwm switching from 0 to 5 v at 100 khz, the low-pass filter time constant is about 0.12 ms and the remaining ripple on the v cp- voltage is about 20 mv. higher values for r cp1 , r cp2 and c cp reduce the ripple, but the reference voltage takes more time to vary after changing the duty cycle of the microcontroller pwm. besides, too high values of r cp1 also increase the impedance of the cp- net at low frequencies, causing a poor noise immunity. as sensing resistor value is typically kept small, a small noise on cp- input pins might cause a considerable error in the output current. it is then recommended to decouple this pin with a ceramic capacitor of some tens of nf, placed very close to cp- and gnd pins. note that cp- pin connected to gnd cannot guarantee zero current due to voltage offset in the internal comparator. the best way to cut down the ic power consumption and to clear the load current is to pull down the diag/en pin. with very small reference voltage, pwm current control method can lose control of the current due to the minimum allowed duration of on-time. r 1 p c c - p c cp- gnd pwm o u tp u t of a c r cp2 am16571v1 v cp- 5v d c r cp2 ?? r cp1 r cp2 + ---------------------------------------------- - =
designing an application with the l6230 AN4243 14/29 doc id 024199 rev 1 2.9 input logic pins inx and enx pins are ttl/cmos and microcontroller compatible logic input pins. the internal structure is shown in figure 10 . typical values for turn-on and turn-off thresholds are v th(on) = 1.8 v and v th(off) = 1.3 v. pins are esd protected and can be directly connected to the logic outputs of a microcontroller; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. figure 10. logic input internal structure diag-en pin has the same input structure with the exception that the drain of the overcurrent and mosfet thermal protection is also connected to this pin. due to this connection, this pin has to be driven very carefully. the en input may be driven in one of two configurations as shown in figure 11 or figure 12 . if driven by an open-drain (collector) structure, a pull-up resistor r en and a capacitor c en are connected as shown in figure 11 . if the driver is a standard push-pull structure the resistor r en and the capacitor c en are connected as shown in figure 12 . the resistor r en should be chosen in the range from 2.2 k to 180 k . recommended values for r en and c en are respectively 10 k and 5.6 nf. more information on selecting the values is found in section 2.10 . 5v e s d protection am16572v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 15/29 figure 11. pin diag/en open collector driving figure 12. pin diag/en push-pull driving 2.10 overcurrent protection to implement an overcurrent protection, a dedicated overcurrent detection (ocd) circuitry (see figure 13 for a simplified schematic) senses the current in each high-side. power dmos are actually made of thousands of individual identical cells, each carrying a fraction of the total current flowing. the current sensing element, connected in parallel to the power dmos, is made of only a few cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element according to the cell ratio. sensed current is, then, a small fraction of the output current and does not contribute significantly to power dissipation. 5v 5v open collector output r en c en diag-en e s d protection am1657 3 v1 5v pu s h-pull output r en c en diag-en e s d protection am16574v1
designing an application with the l6230 AN4243 16/29 doc id 024199 rev 1 figure 13. l6230 overcurrent detection simplified circuitry this sensed current is compared to an internally-generated reference to detect an overcurrent condition. an internal open-drain mosfet turns on when the sum of the currents in the bridge 1, the bridge 2 or the bridge 3 reaches the threshold (2.8 a typical value); the open-drain is available at the diag-en pin for diagnostic purposes and to ensure an overcurrent protection, connecting an rc network (see figure 13 ). figure 14 shows the device operating in overcurrent condition. when an overcurrent is detected the internal open-drain mosfet pulls the diag-en pin to gnd, switching off all 6 power dmos of the device and allowing the current to decay. under a persistent overcurrent condition, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 13 ) reduces the rms value of the output current by imposing a fixed disable time after each overcurrent occurrence. the values of r en and c en are selected to ensure proper operation of the device under a short-circuit condition. when the current flowing through the high-side dmos reaches the ocd threshold (2.8 a typ.), after an internal propagation delay (t ocd(on) ) the open-drain starts discharging c en . when the diag-en pin voltage falls below the turn-off threshold (v th(off) ) all the power dmos turn off after the internal propagation delay (t d(off)en ). the current begins decaying as it circulates through the freewheeling diodes. since the dmos are off, there is no current flowing through them and no current to sense so the ocd circuit, after a short delay (t ocd(off) ), switches the internal open-drain device off, and r en can charge c en . when the voltage at diag-en pin reaches the turn-on threshold (v th(on) ), after the t d(on)en delay, the dmos turn on and the current restarts. even if the maximum output current can be very high, the external rc network provides a disable time (t disable ) to ensure a safe rms value (see figure 14 ). + over temperature i ref i 1 +i 2 / n i 1 / n high s ide dmo s power s en s e 1 cell power s en s e 1 cell power s en s e 1 cell power dmo s n cell s power dmo s n cell s power dmo s n cell s out 1 out 2 v s a out 3 v s b i 1 i 2 i 3 i 2 / n ocd comparator to gate logic internal open-drain r d s (on) 40 typ. c en r en diag-en v dd c or logic i 3 / n + i 3 am16575v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 17/29 figure 14. overcurrent operation timing the maximum value reached by the current depends on its slew-rate, thus on the state of short-circuit, the supply voltage, and on the total intervention delay (t delay ). it can be noticed that after the first current peak, the maximum value reached by the output current becomes lower, because the capacitor on diag-en pins is discharged starting from a lower voltage, resulting in a shorter t delay . the following approximate relations estimate the disable time and the first ocd intervention delay after the short-circuit (worst case). the time the device remains disabled is: equation 11 where equation 12 the total intervention time is: equation 13 where equation 14 t ocd(off) , t ocd(on) , t d(on)en , t d(off)en , and r opdr are device intrinsic parameters, v dd is the pull up voltage applied to r en . o u tp u t c u rrent v th(off) t d(off)en i s over t ocd(on) t di s able t ocd(off) t delay t en(fall) t en(ri s e) v en(low) o u tp u t c u rrent t di s able v th(on) t d(on)en diag-en diag-en am16576v1 t disable t ocd off () t en rise () t don () en ++ = t en rise () r en c en i n v dd v en low () ? v dd v th on () ? ------------------------------------------- ?? = t delay t ocd on () t en fall () t doff () en ++ = t en fall () r opdr c en i n v dd v th off () ------------------------ - ?? =
designing an application with the l6230 AN4243 18/29 doc id 024199 rev 1 the external rc network, c en in particular, must be chosen obtaining a reasonable fast ocd intervention (short t delay ) and a safe disable time (long t disable ). figure 15 shows both t disable and t delay as a function of c en : at least 100s for t disable are recommended, keeping the delay time about 1 to 2s at the same time. figure 15. typical disable time vs. c en (on varying r en ) figure 16. typical delay time vs. c en the internal open-drain can also be turned on if the device experiences an overtemperature (ovt) condition. the ovt causes the device to shut down when the die temperature exceeds the ovt threshold (t j > 165 c typ.). since the ovt is also connected directly to the gate drive circuit (see figure 1 ), all the power dmos shut down, even if diag-en pin voltage is still over v th(off) . when the junction temperature falls below the ovt turn-off threshold (150 c typ.), the open-drain turns off, c en is recharged up to v th(on) and then the power dmos are turned back on. 2.11 thermal management in most applications, the power dissipation in the ic is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. therefore, it has to be taken into account very carefully. besides, the available space on the 1 10 100 1 10 100 1 . 10 3 c en [n f ] t di s able [ s ] r en = 220 k r en = 100 k r en = 47 k r en = 33 k r en = 10 k am16577v1 110100 0.1 1 10 t delay [ s ] c en [n f ] am1657 8 v1
AN4243 designing an application with the l6230 doc id 024199 rev 1 19/29 pcb, the right package should be chosen considering the power dissipation. heat sinking can be achieved using copper on the pcb with proper area and thickness. for instance, using a vfqfpn32l 5 x 5 package the typical r th(ja) is about 42 c/w when mounted on a double-layer fr4 pcb with a dissipating copper area of 0.5 cm 2 on the top side plus 6 cm 2 ground layer connected through 18 via holes (9 below the ic). otherwise, using a power-so package with copper slug soldered on a 1.5 mm copper thickness fr4 board with 6 cm 2 dissipating footprint (copper thickness of 35 m), the r th(ja) is about 35 c/w. using a multi-layer board with vias to a ground plane, the thermal impedance can be reduced down to 15 c/w. 2.12 brake in general, motor braking can be achieved making a short-circuit across the windings: the bemf forces a current, proportional to the braking torque that flows in the opposite direction than in normal running mode. for high bemf and inertia moment, the current may reach very high values: a power resistor is often used to reduce the maximum braking current and dissipate the motor energy. in the l6230, brake function can be achieved to quickly stop the motor while it is running: providing a high logic level to the three in pins all the high-side dmos switch on, making a short-circuit across the motor windings. a power resistor is not used: while the motor is braking, both thermal and overcurrent protections still work, avoiding bemf to cause a current exceeding the device's maximum ratings. using a rc network (see section 2.10 ) a disable time between each overcurrent event can be set, reducing the maximum rms value of the current. figure 17 shows what happens if the current exceeds the ocd threshold while the motor is braking: as soon as the current, in one of the three motor phases, reaches the ocd threshold (2.8 a typ.), the open-drain mosfet internally connected to the diag-en pin discharges the external capacitor; the diag-en pin voltage falls to gnd and all the bridges of the device are disabled for a time that depends on the rc network values. during this disable time, the current, forced by the bemf decreases and so the braking torque; when the current becomes zero (because the motor inductances have been fully discharged), if the bemf is less than the supply voltage there is no braking effect (since the freewheeling diodes cannot be turned on) until the disable time expires and all the high-side power dmos turn on again.
designing an application with the l6230 AN4243 20/29 doc id 024199 rev 1 figure 17. example of overcurrent during motor braking figure 18. example of overcurrent waveforms during motor braking on-time brakin g overcurrent-di s able time am16579v1 i 1 en-diag i 2 i 3 ?brake? command am165 8 0v1
AN4243 application information doc id 024199 rev 1 21/29 3 application information here below some general suggestions for applications based on the l6230 three-phase bldc motor driver. a high quality ceramic capacitor (c 2 ) in the range of 100 nf to 200 nf should be placed between the power pins v sa and v sb and ground near the l6230 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. the capacitor (c en ) and resistor (r en ) connected between the diag-en input and ground set the delay time and disable time when an overcurrent is detected (see section 2.10 ). the current sensing inputs (sense x ) should be connected to the sensing resistors r sense with a trace length as short as possible in the layout. the sense resistors should be non- inductive resistors to minimize the di/dt transients across the resistors. to increase noise immunity, unused logic pins are connected either to 5 v (high logic level) or gnd (low logic level). the power ground and signal ground have to be kept separated on pcb. in ta b l e 2 , recommended values are reported for external components. table 2. component values for typical applications component value description c 1 100 f bulk capacitor c 2 100 nf supply voltage ceramic capacitor (one for v s pins) c boot 220 nf bootstrap capacitor connected between v boot and v s (charge pump) c en 5.6 nf capacitor connected to diag-en pin c p 10 nf fly capacitor connected to cp pin (charge pump) d 1 1n4148 charge pump diode d 2 1n4148 charge pump diode r en 100 k resistor connected to diag-en pin
application information AN4243 22/29 doc id 024199 rev 1 3.1 field oriented control driving method the field oriented control (f.o.c.) method allows smooth and precise motor control of bldc motors to be provided. in this configuration (see figure 19 ), three sensing resistors are required, one for each channel. the sensing signals, coming from the output power stage, are conditioned by external operational amplifiers which provide the proper feedback signals to the analog-to-digital converter and the system controller. according to the feedback signals the six input lines are generated by the controller. note that some filtering and level shifting rc networks should be added between the sense resistor and the correspondent op-amp input. the uncommitted internal comparator with open-drain output is available. figure 19. f.o.c. typical application en 3 out 1 cp+ cp- gnd cpout out 3 out 2 v s a power ground s ignal ground + - v s 8 -52v dc v s b vcp vboot c p c boot d 2 d 1 c 1 c 2 s en s e 1 r s en s e diag/en c en r en enable in 3 en2 in2 en1 in1 en 3 in 3 en2 in2 en1 in1 s en s e 2 s en s e 3 three-pha s e motor m r s en s e r s en s e + - s ign a l conditioning adc am165 8 1v1
AN4243 application information doc id 024199 rev 1 23/29 3.2 six-step driving method with current control the input sequence is generated by the external controller and the l6230 comparator is used to obtain the information for the peak current control. in this configuration, only one sense resistor is needed, the three out pins are connected together to r sense (see figure 20 ). the non-inverting input comparator cp+ monitors the voltage drop across the external sense resistor connected between the source of the three lower power mos transistors and ground. as the current in the motor increases the voltage across, the r sense increases proportionally. when the voltage drop across, the sense resistor becomes greater than the reference voltage applied to inverting input cp- the comparator open-drain output is switched on pulling down the cpout pin. this signal could be managed by controller to generate the proper input sequence for six- step driving method with current control and select what current decay method to implement. when the sense voltage decreases below the cp- voltage, the open-drain is switched off and the voltage at cpout pin increases charging the capacitor c 3 . the reference voltage at pin cp- is set according to the sense resistor value and the desired regulated current: equation 15 a very simple way to obtain a variable voltage is to low-pass filter a pwm output of a controller (refer to section 2.8 ). figure 20. six-step with current control typical application v cp- r sense i target ? en 3 out 1 cp+ cp- gnd cpout out 3 out 2 v s a power ground s ignal ground pwm from controller + - v s 8 -52v dc v s b vcp vboot c cp- r cp- c cpout r cpout c boot d 2 d 1 c 1 s en s e 1 r s en s e diag/en c en r en enable in 3 en2 in2 en1 in1 en 3 c u rrent control s ign a l in 3 en2 in2 en1 in1 s en s e 2 s en s e 3 three-pha s e motor m am165 8 2v1
application information AN4243 24/29 doc id 024199 rev 1 3.3 six-step driving method with bemf zero crossing detection to implement a sensorless motor control system, the information on rotor position is achieved by bemf zero-crossing detection; in this way, no hall-effect sensors or encoders are needed. in six-step driving mode one of the three phases is left in high-impedance state. comparing the voltage of this phase with the motor neutral point voltage (or star point) we can detect the bemf zero-crossing. this information about the commutation between two consecutive steps allows the rotor synchronization to be achieved. in the example of figure 21 , the out1 phase voltage is monitored by the cp+; the center- tap voltage is obtained as combination of three phase voltages and monitored by the cp- pin (r 2 >> r 1 ). only when the out1 is in high-impedance, the cpout performs a commutation each time a bemf zero crossing is detected. in this configuration one sense resistor is needed, the three out pins are connected together to r sense . figure 21. six-step with zero crossing detection typical application en 3 out 1 cp+ cp- gnd cpout out 3 out 2 v s a power ground s ignal ground + - v s 8 -52v dc v s b vcp vboot c p c boot d 2 d 1 c 1 c 2 s en s e 1 r s en s e diag/en c en r en enable in 3 en2 in2 en1 in1 en 3 zero cro ss ing s ign a l in 3 en2 in2 en1 in1 s en s e 2 s en s e 3 three-pha s e motor m r 2 r 2 r 2 r 1 3 r 1 3 r 1 3 r 1 r 2 r 3 am165 83 v1
AN4243 demonstration boards doc id 024199 rev 1 25/29 4 demonstration boards 4.1 eval6230qr demonstration board a demonstration board has been produced to help the evaluation of the device in vfqfpn32l 5 x 5 mm package. it implements a typical application which can be used as a reference design to drive three- phase brushless dc motors with currents up to 1 a dc. thanks to the small footprint of the l6230q the pcb is very compact (32 x 31 mm). for more details on the eval6230qr, refer to the application note an3244. figure 22. demonstration board
demonstration boards AN4243 26/29 doc id 024199 rev 1 4.2 steval-ifn003v1:pmsm foc motor driver based on the l6230 and stm32f103 the steval-ifn003v1 demonstration board is based on the dmos fully integrated three- phase motor driver l6230 and stmicroelectronics' arm? cortex-m3 core-based stm32f103 microcontroller implementing field-oriented control of a pmsm motor. the board is designed as an evaluation environment for motor control applications in the range of 8 v - 48 v of dc bus voltage and up to 45 w, exploiting the computational power of the stm32f103. the l6230 dmos driver features 2.8 a output peak current, non-dissipative overcurrent detection/protection, cross-conduction protection, uncommitted comparator, thermal shutdown and undervoltage lockout. the steval-ifn003v1 is provided with a specific usb interface for the real-time data exchange. offering dedicated hardware evaluation features, the steval-ifn003v1 board is designed to allow developers to evaluate the device and develop their own applications. the steval- ifn003v1 can be used together with the stm32 pmsm single/dual foc sdk v3.0 and constitutes a complete motor control evaluation and development platform. for more details on the steval-ifn003v1 refer to the user manual um1478. figure 23. steval-ifn003v1 board
AN4243 demonstration boards doc id 024199 rev 1 27/29 4.3 steval-ifn004v1:bldc six-step motor driver based on the l6230 and stm8s105 the steval-ifn004v1 demonstration board is based on the dmos fully integrated three- phase motor driver l6230 and stmicroelectronics' stm8s105 microcontroller implementing 6-step scalar control of a bldc motor. the board is designed as an evaluation environment for motor control applications in the range of 8 v - 48 v of dc bus voltage and up to 35 w, exploiting the embedded features of the stm8s105. the l6230 dmos driver features 2.8 a output peak current, non-dissipative overcurrent detection/protection, cross-conduction protection, internal comparator used for cycle-by- cycle current limitation/regulation, thermal shutdown and undervoltage lockout. the steval-ifn004v1 is provided with a specific bemf detection network with dynamic method selection. offering dedicated hardware evaluation features, the steval-ifn004v1 board is designed to help developers evaluate the device and develop their own applications. the steval- ifn004v1 can be used together with the stm8sxxx three-phase bldc motor control software library and constitutes a cost-effective complete motor control evaluation and development platform. for more details on the steval-ifn004v1 refer to the user manual um1477. figure 24. steval-ifn004v1 board
revision history AN4243 28/29 doc id 024199 rev 1 5 revision history table 3. document revision history date revision changes 29-jan-2013 1 initial release.
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